Energy-Aware Compilation for Embedded Processors with Technology Scaling Considerations

With scaling of technology feature sizes, the share of leakage in total energy consumption of digital systems is on the rise. Conventional dynamic voltage scaling (DVS) techniques fail to accurately address the impact of scaling on system energy consumption breakdown, and hence, are incapable of achieving energy efficient solutions in all technology nodes. To overcome this problem, we propose utilizing adaptive body biasing (ABB) to adjust transistors’ threshold voltage at runtime. While ABB has intrinsic limitations with deep sub-micron scaling, we demonstrate that it can be favorably combined with DVS to reduce overall energy consumption down to 45 nm technology node. We develop a leakage-aware compilation methodology for embedded applications under hard or soft timing constraint. Our technique targets embedded processors with both DVS and ABB capabilities, and has the unique advantage of jointly optimizing active and leakage energy dissipation. Considering the delay and energy overhead of switching between operating modes of the processor and execution deadline constraints, our compiler improves the energy consumption of the generated code by average of 21 66% at 90 nm. While our technique’s improvement in energy dissipation over conventional DVS is small (6 43%) at 130 nm, the average improvement continues to grow to 12 23%, 18 63% and 22 16% for 90 nm, 65 nm and 45 technology nodes, respectively. Extensive experiments validate the effectiveness of our approach, explore the involved trade-offs, and offer insights into future trends with respect to technology scaling.